Course Outline


SESI DISEMBER 2018
 
COURSE LEARNING OUTCOMES (CLO)

Upon completion of this course, students should be able to:-

1. Apply the knowledge of various number systems codes, logic operations and logic gates in digital systems. (C3, PL01)

2. Design combinational or sequential logic circuits using Boolean algebra or Karnaugh Map. (C5, PLO4)

3. Manipulate the design of logic diagrams, truth tables and timing diagrams for logic gates and flip-flops and implement them in combinational and sequential logic circuits. (P4, PLO5)

STUDENT LEARNING TIME (SLT)

NO
TOPICS
LECTURES
(HOURS)
PRACTICAL
(HOURS)
ASSESSMENT
(HOURS)
INDEPENDENT LEARNING
(HOURS)
1.0
NUMBER SYSTEMS AND CODES
Decimal, binary, octal and hexadecimal number systems; Two’s complement systems; BCD 8421 and ASCII Code.
6
0
5
(Quiz, Test, Practical Work),
Final Exam – 2
78
(End Of Chapter -10,
Preparation Lecture – 30,
Preparation Lab – 22,
Preparation Test – 4, Preparation Practical Test – 4, Preparation F.A – 8)
 
2.0
BOOLEAN OPERATIONS
Symbols, truth table, logic gates applications; NOT, AND, OR, NOR, NAND, XOR, XNOR. Laws of Boolean Algebra, Sum of Product (SOP), Product of Sum (POS) and Karnaugh Map.
9
8
3.0
DATA PROCESSING CIRCUITS
Encoder, Decoder, BCD to Seven Segment Display Decoder,
Multiplexer and Demultiplexer.
6
8
4.0
FLIP-FLOPS
Types of flip-flops: SR flip-flop, clocked SR flip-flop, T flip-flop, D flip-flop and JK flip-flop. Symbols, truth tables and timing.
9
8
5.0
COUNTERS
Basic concepts of asynchronous and synchronous counters; logic circuits and timing diagram of counter. Various types of asynchronous and synchronous counters.
6
4
6.0
REGISTERS
Basic concepts of registers and shift registers; classification of shift registers; arithmetic circuit; integrated circuit of shift registers; Ring counters and Johnson counter.
9
4
 
 
TOTAL HOURS
45
30
7
78
SLT (Hours)
160
Credit = SLT/40
4

 

ASSESSMENT

1. Coursework Assessment (CA) - 50%

i. Theory Test - 20%

ii. Quiz - 10%

iii. Practical Work - 50%

iv. End Of Chapter - 10%

v. Practical Test – 10%

2. Final Exam - 50%

 

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